Welcome
Welcome to the RISC-V Ratified Specs guide. This page collects ratified specifications mirrored by RuyiSDK, so you can start from your area of interest and then open the original documents when implementation details matter.
RISC-V includes the base/user-level instruction set architecture (Unprivileged ISA) and the privileged architecture (Privileged ISA), and it also covers platform software, hardware interfaces, debug and trace, and application enablement.
A Ratified Spec is a specification version that has been formally approved by RISC-V International.
Being ratified and being merged into a publicly released specification document do not always happen at the same time. On the RISC-V Technical Hub Ratified ISA Extensions page, linked entries indicate extensions that have been ratified but not yet merged into the final documents published in the Ratified Specifications Library. Entries without links can usually be found in the publicly released specification documents.
You can start from the engineering problem you are facing, then jump into the matching specification category.
Start with the execution model visible to regular programs, privilege levels, exceptions, and interrupts.
System software / firmwareCategory: Platform SoftwareLook first at boot, SBI, UEFI, and platform management interfaces used in system enablement work.
Software ecosystem compatibilityCategory: ProfilesUse Profiles to understand the baseline capability sets expected by software.
Hardware / SoC / validationCategory: HardwareFocus on platform integration and hardware interfaces such as IOMMU, PLIC, Server SoC, and QoS.
Debug / trace / bring-upCategory: Debug, Trace, and RASStart from the debug model, trace data, and error record interfaces for low-level diagnosis.
Compilers / runtimes / vector librariesCategory: Application EnablementFocus on ABI, semihosting, and vector intrinsics for porting and optimization work.
Foundational material for processors, instructions, privilege levels, and interrupts.
RISC-V Interrupts
Summary: Explains RISC-V interrupt mechanisms for consistent interrupt handling across hardware and system software.
Audience: Useful for kernels, firmware, chips, interrupt controllers, and platform enablement developers.
RISC-V Platform-Level Interrupt Controller
Summary: Defines platform-level interrupt controller behavior for managing external device interrupts.
Audience: Useful for kernels, firmware, SoCs, boards, and interrupt subsystem developers.
RISC-V Privileged Architecture
Summary: Explains privilege levels, exceptions, interrupts, page tables, and system registers for operating systems.
Audience: Useful for OS, virtualization, firmware, simulator, and processor implementation developers.
RISC-V Unprivileged Architecture
Summary: Describes instructions, registers, and execution models visible to regular programs.
Audience: Useful for RISC-V learners, compilers, simulators, processor implementations, and application porting.
Capability sets that help software reason about platform compatibility.
RISC-V Profiles
Summary: Defines RISC-V platform capability sets so software can reason about expected baseline features.
Audience: Useful for distributions, toolchains, platform enablement, and compatibility work.
RVA23 Profile
Summary: Defines capability sets for application-processor platforms to give software a consistent target.
Audience: Useful for distributions, application-processor platforms, toolchains, system software, and compatibility testing.
RVB23 Profile
Summary: Defines RVB23 platform capability sets for software and hardware adaptation.
Audience: Useful for embedded platforms, toolchains, platform enablement, and compatibility validation.
Hardware implementation topics for SoCs, devices, IOMMU, server platforms, and resource management.
RISC-V IOMMU MSI Translation Specification
Summary: Describes MSI interrupt translation mechanisms for IOMMU scenarios on complex I/O and virtualization platforms.
Audience: Useful for IOMMU, device, interrupt, virtualization, and SoC platform developers.
RISC-V Capacity and Bandwidth QoS Register Interface
Summary: Defines register interfaces for capacity and bandwidth quality-of-service management.
Audience: Useful for SoC, server platform, resource isolation, QoS, and performance management developers.
RISC-V IOMMU
Summary: Defines RISC-V IOMMU functionality and interfaces for device address translation, isolation, and virtualization.
Audience: Useful for SoC, device, virtualization, OS kernel, and platform security developers.
RISC-V Server SoC
Summary: Describes RISC-V SoC platform requirements for server-class systems.
Audience: Useful for server SoC, platform verification, firmware, kernel, and datacenter hardware developers.
Debugging, execution trace, error records, and reliability-related capabilities.
RISC-V N-Trace Specification
Summary: Describes RISC-V execution trace capabilities for N-Trace and related scenarios, helping tools understand program execution.
Audience: Useful for debugger authors, trace tooling, chip bring-up, and verification engineers.
RISC-V Trace Connectors
Summary: Defines conventions for trace connectors so hardware platforms and external debug equipment can interoperate.
Audience: Useful for debug hardware, boards, probes, and trace tool developers.
RISC-V Trace Control Interface
Summary: Defines interfaces for configuring and managing RISC-V trace behavior from software or debug tools.
Audience: Useful for debug tools, firmware, chip verification, and platform bring-up.
E-Trace Encapsulation
Summary: Specifies how E-Trace data is encapsulated for transport between tools and systems.
Audience: Useful for trace tools, debug interfaces, hardware verification, and data capture systems.
RISC-V Debug Specification
Summary: Defines the RISC-V debug model and interfaces, including breakpoints, single stepping, and register access.
Audience: Useful for debuggers, simulators, chip bring-up, verification, and IDE tooling.
RISC-V Error Record Register Interface
Summary: Defines error record register interfaces for reporting and analyzing hardware errors.
Audience: Useful for RAS, firmware, kernel, server platform, and reliability engineering work.
RISC-V Trace Specification
Summary: Defines core mechanisms for RISC-V execution trace and reconstructing program execution paths.
Audience: Useful for debuggers, performance analysis, trace tools, chip verification, and system bring-up.
System software interfaces for firmware, boot, SBI, UEFI, and platform management.
RISC-V UEFI Protocol Specification
Summary: Describes UEFI protocol conventions for RISC-V platforms and standardized handoff between firmware and operating systems.
Audience: Useful for firmware, boot chains, OS porting, and platform enablement developers.
RISC-V Boot and Runtime Services Specification
Summary: Describes basic boot and runtime service conventions for RISC-V platforms.
Audience: Useful for firmware, bootloaders, OS boot, and platform enablement developers.
RISC-V Firmware Features
Summary: Describes how firmware exposes platform features to upper software layers.
Audience: Useful for firmware, kernels, boot chains, and platform capability discovery work.
RISC-V Platform Management Interface
Summary: Defines platform management interfaces for power, performance, and platform state management.
Audience: Useful for firmware, platform management, kernels, power management, and server systems.
RISC-V Supervisor Binary Interface
Summary: Defines the standard interface between supervisor-mode kernels and machine-mode firmware.
Audience: Useful for kernel, OpenSBI, firmware, virtualization, and OS porting developers.
Toolchain and application support for ABI, porting, semihosting, and vector intrinsics.
RISC-V ABI
Summary: Defines binary interface conventions so compilers, libraries, and applications work together correctly on RISC-V.
Audience: Useful for compiler, runtime, distribution, application porting, and toolchain developers.
RISC-V Semihosting
Summary: Explains how target programs can use host services for I/O and related helper operations.
Audience: Useful for bare-metal applications, debuggers, simulators, teaching, and embedded development.
RISC-V Vector Intrinsic Specification
Summary: Defines C/C++ intrinsic interfaces for using RISC-V vector capabilities in portable code.
Audience: Useful for compilers, performance libraries, HPC, AI inference, media processing, and application optimization.
Note: This page is a guide and mirror download entry. For the corresponding technical standards, please refer to the RISC-V International technical website.